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Senior VLSI Verification Engineer – SystemVerilog UVM Lead
  • Kraków
Senior VLSI Verification Engineer – SystemVerilog UVM Lead
Kraków, Kraków, Lesser Poland Voivodeship, Polska
NeuReality
22. 1. 2026
Informacje o stanowisku

A dynamic technology startup is seeking a Senior Verification Engineer in Kraków, Poland. In this role, you will be responsible for developing verification strategies and executing tests for advanced SoC designs. The successful candidate should have over 7 years of experience in verification engineering, specifically in SystemVerilog UVM, and should possess strong skills in pre-silicon verification. This position offers a unique opportunity to shape the future of AI solutions within a growing team.
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  • Praca Kraków
  • Kraków - Oferty pracy w okolicznych lokalizacjach


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