Informacje o stanowisku

A leading technology company based in Katowice is seeking a Senior Verification Engineer to join their SoC Verification team. The role involves developing System Verilog UVM testbenches, implementing functional coverage models, and ensuring complete design verification. Candidates should have strong proficiency in System Verilog, extensive experience with simulation tools, and excellent communication skills. This position offers various perks, including sharing the costs of sports activities and private medical care.
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