Informacje o stanowisku

A leading technology firm is seeking a Staff Verification Engineer to focus on SoC Verification within their verification team. This role involves developing SystemVerilog-UVM testbenches and contributing to the improvement of the verification strategy. The ideal candidate has over 8 years of experience in SoC verification, strong skills in SystemVerilog and UVM, and excellent communication abilities. Join a team that values diversity and encourages innovative thought in a fast-paced technology environment.
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