Senior Silicon Physical Design Engineer – Axelera AI

Join us as a Senior Silicon Physical Design Engineer at Axelera AI, a next‑generation AI platform company headquartered in Eindhoven, Netherlands. We are building advanced multi‑core in‑memory compute SoCs and need your expertise in ASIC Physical Design from RTL to GDS.

About Us

We are not a typical deep‑tech startup. In just four years we have raised $120 million and built a world‑class team of 220+ employees, including 49+ PhDs with more than 40,000 citations. Our Metis™ AI Platform delivers a 3‑5x boost in efficiency and performance, and we have a strong pipeline exceeding $100 million in revenue.

Position Overview

As a Senior Silicon Physical Design Engineer you will design, verify, and sign‑off SoC physical designs. You will collaborate closely with architecture and RTL teams to ensure project objectives are met.

Key Responsibilities

• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
• Generate timing constraints and perform optimization.
• Execute clock tree synthesis (CTS) and custom clock‑building techniques.
• Integrate IPs (memories, I/Os, embedded processors, DDR, networking fabrics, analog IPs).
• Use EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, and Bash; contribute to flow development.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.

Qualifications

• 10+ years of experience in physical design from RTL to GDS.
• Strong communication and teamwork skills.
• Expertise in all aspects of physical design.
• Hands‑on experience with leading EDA tools.
• Proficiency in clocking techniques and CTS.
• Experience integrating IP across domains.
• Strong scripting skills (Python and Tcl).
• Proven problem‑solving and debugging capabilities.
• Fluent in English (spoken and written).

Highly Preferred

• Experience in floorplanning and top‑level integration.
• Knowledge of chip‑package‑board co‑simulation and packaging.
• Experience working with EDA vendors to resolve tool issues.
• Understanding of semiconductor device physics and multi‑domain design.

Location

• Work from one of our offices in Leuven (Belgium), Amsterdam or Eindhoven (Netherlands), Florence or Milan (Italy), or Bristol (UK) if you are based nearby.
• Fully remote from any European country (including the UK).
• Relocate to Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).

Priority is given to candidates based in Belgium or Italy.

What We Offer

Join a dynamic, fast‑growing, international organization. We provide an attractive compensation package, pension plan, extensive employee insurance, and the option to obtain company shares. An open culture that supports creativity and continual innovation awaits you, with collaborative ownership and freedom with responsibility.

Equal Opportunity

At Axelera AI we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to shape the future of AI.