Senior Principal Design Engineer

Location: Katowice, Poland

Reports to: Design Engineering Director

Job Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence IP Group (IPG) develops leading‑edge Intellectual Property (IP) for a variety of High‑Tech Markets. The Cadence IP solutions allow our Customers to tackle IP‑to‑SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence IP Vision is to deliver industry‑leading IP solutions that enable our customers to succeed in these fast‑moving application spaces. The Sr Principal Design Engineer will be based in Katowice, Poland as part of an experienced Controller IP Team with long established Controller development sites in Europe and India.

Job Responsibilities

• Development of complex IP such as PCIe, UCIe, CXL, Ethernet, MIPI‑Visual
• Development of RTL, Testbenches & FPGA Platforms
• Technically lead small teams/multidiscipline
• Deployment of Front‑end design tools e.g. LINT, Synthesis and CDC Tools
• Support customer pre‑sales and post‑sales meetings
• Participate in Technical Review Meetings and Checklist Reviews as part of ISO‑9001
• Represent Cadence in Standards Body Working Groups e.g. JEDEC, IEEE, PCI‑SIG, MIPI

Job Qualifications

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
• 10+ years’ experience in microelectronics/EDA industry
• Proficient in Verilog coding, RTL design and complex control path and data path designs
• Knowledge of any of the interface Protocols like ONFi, UCIe, PCIe, USB, MIPI, Ethernet
• Experience of Metric Driven Verification (MDV) essential
• Knowledge of RTL checks - LINT, SDC, CDC
• Familiar with synthesis flow, LEC and timing constraintsExperience in writing Verilog testbench and running simulations
• Excellent oral and written English essential
• Self‑motivated with excellent planning, interpersonal, and communication skills

Additional Skills / Preferences

• Experience of AMBA, PCIe, CXL & UCIe protocols preferred
• Experience of Quality processes, such as ISO‑9001 & ISO‑26262 preferred

What We Can Offer You

• Private Health Insurance
• 5 days Volunteering Time off each year
• Employee Stock Purchase Plan
• Competitive salary package adequate to competencies
• Internet Expenses reimbursement
• Competitive Referral Program
• Work from the office or Hybrid Work
• Flexible working hours
• Life insurance
• Multisport Plus cards
• Social Fund benefits
• Recommendation bonuses & Internal recognition program

Additional Information

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Information Technology

Industries

Software Development