Informacje o stanowisku

technologies-expected :

• Python
• Git

• Our multinational technology client is currently seeking a Senior IP Design Engineer to design high-performance IP targeting FPGA and Adaptive SoC technologies, delivering synthesis-ready designs that meet timing and integration requirements.

• Design SystemVerilog RTL for FPGA / Adaptive SoC
• Deliver synthesis-ready IP designs
• Ensure timing closure and integration readiness
• Support FPGA design flow from RTL to P&R
• Collaborate with verification and system teams

• SystemVerilog RTL design
• FPGA / Adaptive SoC design flow
• PCIe, Ethernet, AMBA / AXI
• Vivado / Vitis
• Python / TCL scripting
• Git, CI/CD

Warszawa - Oferty pracy w okolicznych lokalizacjach