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Senior IP Design Engineer
  • Warsaw
Senior IP Design Engineer
Warszawa, Warsaw, Masovian Voivodeship, Polska
DCV Technologies
14. 2. 2026
Informacje o stanowisku

technologies-expected :


  • Python
  • Git

about-project :


  • Our multinational technology client is currently seeking a Senior IP Design Engineer to design high-performance IP targeting FPGA and Adaptive SoC technologies, delivering synthesis-ready designs that meet timing and integration requirements.

responsibilities :


  • Design SystemVerilog RTL for FPGA / Adaptive SoC
  • Deliver synthesis-ready IP designs
  • Ensure timing closure and integration readiness
  • Support FPGA design flow from RTL to P&R
  • Collaborate with verification and system teams

requirements-expected :


  • SystemVerilog RTL design
  • FPGA / Adaptive SoC design flow
  • PCIe, Ethernet, AMBA / AXI
  • Vivado / Vitis
  • Python / TCL scripting
  • Git, CI/CD

  • Praca Warszawa
  • Warszawa - Oferty pracy w okolicznych lokalizacjach


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