Informacje o stanowisku

A leading provider in semiconductor technology is seeking a Design Verification Engineer to work on advanced System‑on‑Chip (SoC) assembly and HSI flows. Candidates will need over 7 years of experience in RTL verification, expertise in the UVM framework, and proficiency in Python scripting. This full-time role is based in Kraków, with a compensation range of 14,000 to 16,500 PLN gross per month, and offers a dynamic work environment focused on quality and commitment.
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