This recruitment process is project-based oriented - it means that after receiving an offer from EndySoft, you will be assigned to work in one specific project for one of our Czech clients from IT sector.
We are currently seeking a seasoned RTL Validation Engineer to join our dynamic team. This role requires substantial experience in RTL design and validation, particularly with Standard IO interfaces like PCIE and CXL. The ideal candidate will have proven expertise in handling complex RTL projects and delivering high-quality results under tight deadlines.
MD rate: 180 - 220 EUR
responsibilities :
Conduct rigorous RTL validation for various designs, focusing on interfaces such as PCIE and CXL.
Develop and implement verification plans to ensure designs meet all functional and performance requirements.
Collaborate with design engineers to understand circuit architectures and create effective test strategies.
Identify, document, and debug RTL issues, and work closely with the design team to resolve them efficiently.
Optimize existing validation processes and methodologies to improve project outcomes and timelines.
Provide detailed reports and documentation related to RTL validation activities and results.
requirements-expected :
Strong background in RTL design and validation, with specific expertise in Standard IO interfaces such as PCIE and CXL.
Several years of experience working in RTL validation, with a proven track record of handling complex projects.
Proficient in verification languages and tools such as SystemVerilog, UVM, and other relevant industry-standard tools.
Excellent problem-solving skills and the ability to work independently in a fast-paced environment.
Strong analytical skills with meticulous attention to detail.
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
