Informacje o stanowisku

In this role, you will collaborate in the development of advanced analog integrated circuit designs using the best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes.

As a member of our Solutions IP Design Group, you will be developing IP in various technology nodes and foundries for different customers in a fast-paced and exciting design environment.

Main Requirements:

• Masters or Bachelors degree in Electronic/Electric Engineering with a strong interest to develop within the area.
• Good understanding of basic electric rules (i.e., resistance, capacitance, inductance).
• Familiarity with silicon physical phenomena and basic active silicon devices behavior.
• A quick learner and a problem-solver.
• Good written and verbal English skills.

Nice to have:

• Familiarity with layout of analog and mixed-signal CMOS circuits.
• 1+ year of relevant work experience.
• Experience in the following layout design techniques:
  • Optimization for signal integrity (i.e., clock/data routes, differential routing, shielding).
  • Implementation of ESD design constraints, latch-up risk mitigation.
  • Familiarity with custom digital layout (logic cell layout and associated logic path routing).
  • Layout design for reliability (i.e., EM, IR, etc.).
  • Design to optimize for parasitic layout effects (i.e., matching, reliability, proximity effects, etc.).
• Full custom analog layout design tool: Custom Compiler (or equivalent).
• Verification tools: ICV, Calibre, Star-RCXT, PERC.
• Experience in working with Jira/Atlassian (or other such tools).
• Exposure to scripting (i.e., TCL, PERL, etc.).

Gdańsk - Oferty pracy w okolicznych lokalizacjach