Informacje o stanowisku

technologies-expected :

• SystemVerilog
• VHDL

• Definition, documentation, development, and execution of simulation based verification test for Arteris Register Bank compiler tool, able to run on any available RTL simulator (Cadence, Synopsys, Siemens).
• Definition, documentation, development, and execution of validation tests using Python scripting for qualifying additional Register tool collaterals (IP-XACT, C Header files, Documentation).
• Maintain and enhance tests in the continuous integration flow, improve metrics, and increase automation.
• Help improve and refine processes, methodologies, and metrics.
• Be familiar with modern tools for specifications/documentation, tasks and project tracking (like Confluence and Jira).
• Collaborate with developers to identify testing needs and scenarios specific to EDA.
• Participate in code reviews and unit testing with other developers to ensure code quality.

• 7+ years of industry experience as RTL verification engineer.
• Strong expertise in UVM framework.
• Understanding of hardware RTL design languages (VHDL, Verilog, SystemVerilog).
• Proficient with Python scripting language.
• Fluent English.
• Engineering degree in computer science or a related field.

• private medical care
• sharing the costs of foreign language classes
• remote work opportunities
• flexible working time
• pre-paid cards

Kraków - Oferty pracy w okolicznych lokalizacjach