Informacje o stanowisku

Junior / Senior & Principal FPGA Design Engineers (Global)

You will have some of the following skills depending on your role :

• Be able to contribute to FPGA architecture proposals as per requirements capture. To this end, knowledge of 5G and ORAN is desirable but not essential.
• Digital frontend design and verification techniques using SystemVerilog/Verilog.
• Implementing functional and code coverage techniques in simulation.
• Implementation of DSP algorithms for FPGA.
• Using Matlab for all aspects of FPGA development from architecture to lab verification.
• Knowledge of interface protocols (Ethernet, DDR4, SPI, etc).
• Strong knowledge of Xilinx and Intel FPGA tool flows.
• C/C++ for FPGA embedded software applications and/or co-simulation.
• Proficient with scripting languages such as TCL or Python.
• Experience of SystemC and UVM is advantageous.
• Experience with lab equipment, e.g., Signal Generator, Signal Analyser.
• Experience of SVN and GIT.

Required Qualifications

The minimum educational requirement is a bachelor’s degree in Electronic / Electrical / Telecommunication Engineering. A Master’s Degree or Ph.D. with relevant emphasis is advantageous.

Minimum 2-3 years experience for mid-level roles and minimum 5 years for senior roles.

You will be responsible for

• Design FPGA systems for radio communication systems including digital front-end DSP such as filters, up and down-conversion.
• Active collaboration with a multidisciplinary team on architecture and design within digital design expertise. Provide inputs to architecture and design reviews.
• Design documentation including product specifications, design descriptions, and test specifications.
• Write, simulate, and verify Verilog/SystemVerilog based FPGA designs.
• Developing API and Software for FPGA bring-up and system-level validation and operation.
• SoC performance and power estimation and optimization, clock, and reset distribution optimization.

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