Informacje o stanowisku

technologies-expected :

• ASIC

• Collaborate with a team of ASIC verifiers to execute IP design/verification and SubSys integration/verification projects.
• Utilize your expertise in ASIC verification to ensure the successful completion of complex projects.
• Work with various levels of experience within the team, providing mentorship and support to junior members.
• Contribute to test bench structuring and design, leveraging your leadership qualities to drive project success.
• Demonstrate proficiency in RTL design, scripting, and telecommunication protocols.

• 3 years or more of experience in ASIC verification.
• Proficiency in UVM for at least one year is preferred.
• Experience working with complex ASIC and/or large FPGA designs.
• Familiarity with IP block verification and multi-clock domains.
• Strong proficiency in Verilog, VHDL, and/or SystemVerilog.
• Excellent English communication skills, both verbal and written.
• Leadership qualities and the ability to mentor junior team members.
• Scripting skills for test automation.

• Competitive compensation package.
• Remote work opportunities within European time zones.
• Occasional travel to Sweden, with expenses covered by the client.
• Collaborative and dynamic work environment.
• Opportunities for professional growth and development.

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