Informacje o stanowisku

junior specialist (Junior), specialist (Mid / Regular)

• work on projects for the largest players in ASIC world,
• verify digital circuits using SystemVerilog language and the most modern ASIC verification methodology - UVM,
• work on a structured and well planned projects (we use Requirements Based Development Processes in our projects).

Our requirements

• at least 2-3 years of relevant experience (verification of ASIC/FPGA using SystemVerilog)
• very good knowledge of English that allows everyday communication and documentation creation,
• very good understanding of Digital Design principles,
• very good understanding of SoC,
• knowledge of SystemVerilog,
• good knowledge of Object Oriented Programming,
• ability and willingness to learn and work as part of a team,
• a valid work permit for Poland/European Union.
• knowledge of communication interfaces such as I2C, SPI, AHB
• understanding of configuration management and change management principles,
• knowledge of scripting languages,
• experience of using modern simulation tools (Modelsim/Questa, Simvision).

This is how we organize our work

Team size

• 5

This is how we work

• at the clients site
• you focus on a single project at a time
• you develop the code "from scratch"

This is how we work on a project

• functional tests
• regression tests
• testing environments

Development opportunities we offer

• substantive support from technological leaders
• technical knowledge exchange within the company

What we offer

• competitive salary package adequate to competencies,
• full employment contract,
• working on challenging projects,
• support of senior engineers to allow you quickly gain technical experience,
• logicBC is a company that provides ASIC/FPGA design and verification services in the Aerospace and Automotive industries. At the moment we are looking for engineers to work with us on ASIC verification project for our client.

Gliwice - Oferty pracy w okolicznych lokalizacjach