Project duration: 12 months with possibility of extension
Salary: 170-195PLN/h netto + VAT
responsibilities :
Lead ASIC Development Projects: Oversee and guide the development of complex ASIC and large FPGA designs, ensuring they meet technical specifications and project timelines.
Design and Implement Multi-Clock Domain Solutions: Work with multi-clock domains to develop efficient and optimized system architectures.
Systemization and Architecture Design: Contribute to the systemization process, leading the design of system architectures in line with project requirements.
Utilize System Verilog for Design and Verification: Apply expertise in System Verilog for developing and verifying ASIC and FPGA designs.
Manage Backend Processes: Handle backend tasks such as setting timing constraints, timing optimization, and performing formal verification to ensure the integrity of designs.
Conduct UVM Verification: Implement Universal Verification Methodology (UVM) to verify the functionality of complex designs.
Script Development: Utilize scripting skills for automation and optimization of design processes.
Use Spyglass for Static Verification: Leverage Spyglass to perform static analysis, ensuring design quality and adherence to industry standards.
requirements-expected :
You have a solid background with more than 5+ years of experience of ASIC development.
Used to work with complex ASIC and/or large FPGA design.
Multi clock domains.
System Verilog.
Experience of systemization and architecture design.
Leadership qualities.
Backend work with timing constraints, timing optimization and formal verification.
