Hardware Design Verification Engineer - IP Development for Network-on-Chip

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system‑on‑chips (SoCs) that fuel modern innovation.

Arteris’s role will entice you:

Key Responsibilities

• Define, document, develop and execute RTL verification test/coverage for extremely parameterized IPs in Python and C++, capable of running on any available RTL simulator (Cadence, Synopsys, etc.).
• Maintain and improve verification workflow, improve metrics and increase automation.
• Implement verification components such as BFMs or monitors used in verification test benches.

Required Experience / Qualifications

• At least 2 years of industry experience as a verification engineer.
• Understanding of hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog).
• Strong experience in the use and development of verification methods and infrastructure (VIPs, UVMs, testbeds, EDA tools).
• Experience in formal proof verification methodology is a plus.
• Shell scripting.
• Knowledge of interconnect technology is a plus.
• Understanding of hardware communication protocols (AMBA, OCP, others).
• Good written and oral communication in French and English.
• Curious, autonomous, rigorous and results‑oriented, with a commitment to quality and a thorough approach to work.
• Proven ability to work well in a team environment.

Educational Requirements

• Master’s degree or Doctorate in engineering or computer science.

Arteris is a leading provider of system IP for the acceleration of system‑on‑chip (SoC) development across today’s electronic systems. Arteris network‑on‑chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.

With over 250 employees, headquartered in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.

Seniority level: Entry level.

Employment type: Full‑time.

Job function: Engineering and Information Technology.

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